The present invention relates to computer chips for controlling access to a cache memory.
In International Business Machine (IBM) compatible personal computers, the refresh controller sends out one refresh address every 15 microseconds. Each refresh cycle takes around 1 microsecond to refresh all of the system's dynamic memory. In order to keep valid data in dynamic random access memory (RAM), 256 refresh cycles are required every four milliseconds. To enter the refresh cycle, a refresh counter sends out one refresh request every 15 microseconds and a hold request signal is then sent back to the CPU to relinquish the bus to the refresh controller. The CPU regains the bus after the refresh cycle is done.